1. Field of the Invention
The present invention relates to computer systems and, more specifically but not exclusively, to the handling of interrupt-triggering events in computer systems.
2. Description of the Related Art
This section introduces aspects that may help facilitate a better understanding of the invention. Accordingly, the statements of this section are to be read in this light and are not to be understood as admissions about what is prior art or what is not prior art.
The architecture of a conventional node in a data network has a data plane and a control plane. The data plane is configured to handle normal processing of an incoming data stream to produce a corresponding outgoing data stream. At times, events occur that require special processing. Typical events include, without limitation, MAC (media access control) learning, OAM (operations, administration, and maintenance)-related state changes, counter overflows. In conventional nodes, such events are processed as hardware interrupts, where the control plane performs the required special processing for such hardware interrupts.
A conventional node is provisioned with an interrupt buffer of a finite size. Each instance that the data plane detects an event requiring special handling, the data plane adds a hardware interrupt to the interrupt buffer. Concurrently, the control plane processes hardware interrupts stored in the interrupt buffer on a first-in, first-out basis.
If hardware interrupts are added to the interrupt buffer by the data plane faster than the control plane can process those hardware interrupts, the interrupt buffer may become temporarily full, thereby preventing any additional hardware interrupts from being added to the interrupt buffer until the interrupt processing of the control plane frees up sufficient space in the interrupt buffer. Such interrupt-buffer overflow results in one or more new hardware interrupts being dropped by the node, thereby failing to perform the special processing required to handle the events that triggered those dropped hardware interrupts. The failure to perform the required special processing for some types of events that trigger hardware interrupts (e.g., MAC learning or OAM-related state change) may be inconsequential, but not for all types of interrupt-triggering events. For some types of events (e.g., counter overflow), the failure to perform the required special processing can be catastrophic to the proper functioning of the node and possibly of the entire network.